`timescale 5ns/5ns

module baudgen_t_baudgen_v_tf();

// DATE:     17:07:53 09/19/2006 
// MODULE:   baudgen
// DESIGN:   baudgen
// FILENAME: t_baudgen.v
// PROJECT:  spart
// VERSION:  


// Inputs
    reg clk;
    reg rst;
    reg iorw;
    reg iocs;
    reg [1:0] ioaddr;
    reg [7:0] divin;


// Outputs
    wire transrateen;
    wire recvrateen;


// Bidirs


// Instantiate the UUT
    baudgen uut (
        .clk(clk), 
        .rst(rst), 
        .iorw(iorw), 
        .iocs(iocs), 
        .ioaddr(ioaddr), 
        .divin(divin), 
        .transrateen(transrateen), 
        .recvrateen(recvrateen)
        );


// Initialize Inputs
    `ifdef auto_init

        initial begin
            clk = 0;
            rst = 0;
            iorw = 0;
            iocs = 0;
            ioaddr = 0;
            divin = 0;

		  #10 rst = 1'b1;
		  
		  #10 
		  rst = 1'b0; 
		  iorw = 1'b0;
		  iocs = 1'b1;
		  ioaddr = 2'b10;
		  //program the lower byte
		  divin = 8'd3;
		  
		  #10
		  ioaddr = 2'b11;
		  //program the upper byte
		  divin = 8'd1;
		  		  		  

        end

    `endif

always @(*)
	clk = ~clk;




endmodule

